AMD patent list that was published recently. Some Zen3 and CDNA foundation patents in the mix. AMD is also ramping up its Exascale Heterogenous Processor (EHP) IP.
Side information for video data transmission : Methods for performing efficient video compression for wireless VR stream communication
Integrated circuit package with integrated voltage regulator : Looks like next gen CPU/GPU need an integrated voltage regulator
Auto generation and tuning tool for convolution kernels : Methods for implementing an auto generation and tuning tool for convolution kernels, which is a basic CDNA foundation.
Processing unit with mixed precision operations : More CDNA goodies.
Using Multiple Memory Elements in an Input-Output Memory Management Unit for Performing Virtual Address to Physical Address Translations : This has some potential for speeding up access to Storage class memory device.
Multi-RDL structure packages and methods of fabricating the same : next CPU battlefield is the packaging tech
Detecting voice regions in a non-stationary noisy environment : Foray into mobile phone tech, or simply wants to compete with NVDIA RTX voice?
Fan-Out packages with warpage resistance : packaging, packaging, packaging
Method and apparatus for peer-to-peer messaging in heterogeneous machine clusters : this one is interesting, looks like thread aware RDMA type semantics… foundation for EHP
Pipeline including separate hardware data paths for different instruction types : Say hello to one of the Zen 3 foundations…
Implementing a micro-operation cache with compaction : Say hello to one of the Zen 3 foundations…
Home agent based cache transfer acceleration scheme : Systems, apparatuses, and methods for implementing a speculative probe mechanism
Probe placement for laser probing system : A great improvement in defect identification
Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers : remember the “zero-bubble” branch prediction, this is a continuation of the same idea. In case you didn’t know a bubble in the core pipeline is when it’s idle either due to a memory stall or incorrect branch prediction wherein the entire pipeline has to be flushed and loaded with a new set of instructions, wasting precious execution cycles.
Method enabling virtual pages to be allocated with noncontiguous backing physical subpages : ho…. this one is interesting, virtual page backed by fragmented physical page. Not sure of the practical use case but this can lead to some interesting stuff in the virtualization domain.
Precise suspend and resume of workloads in a processing unit : A method for support suspend/resume operations for dependent workloads executing on different pipelines in GPUs
Stochastic rounding logic : Techniques and circuits are provided for stochastic rounding. Highly recommended to read the article referred to in the patent.
Near-memory hardened compute blocks for configurable computing substrates : EHP foundations … keep a close eye on this one.
In-memory interconnect protocol configuration registers : More EHP foundation
Source clock recovery in wireless video systems : wireless console video ? probably VR/AR tech.
Platform Agnostic Atomic Operations : Atomic operations for GPU or FPGA… RDMA semantics, I see what you are doing here AMD, more EHP foundation
Deskewing method for a physical layer interface on a multi-chip module : packaging interconnect
Memory management in graphics and compute application programming interfaces : continuation of U.S. patent application Ser. No. 15/477,795, filed Apr. 3, 2017
Virtual Reality Beamforming : Methods for implementing enhanced beamforming training procedures in VR wireless communication.
Wave creation control with dynamic resource allocation : A method to determine the resource allocations of waves based on the average resource allocation and dispatching the spawned waves on the GPU.
Swizzling In 3D Stacked Memory : EHP …
Processor with accelerated lock instruction operation : Another Zen3 foundation…
Hybrid Matrix Multiplication Pipeline : More CDNA
Compressing tags in software and hardware semi-sorted caches : A data storage system which performs partial compression and decompression of cached data.
Semiconductor chip with stacked conductor lines and air gaps: Air gaps in interlevel dielectric layers between adjacent conductor lines to counteract the capacitance increase associated with reduced line spacing.